This invention relates generally to transistors, and more particularly, to a compact memory transistor cell.
Metal-oxide-Semiconductor field effect transistor (MOSFET) technology is the dominant electronic device technology in use today. Performance enhancement between generations of devices is generally achieved by reducing the size of the device, resulting in an enhancement in device speed. This is generally referred to as device “scaling”. As MOSFETs are scaled to channel lengths below 100 nm, conventional MOSFETs suffer from several problems. In particular, interactions between the source and drain of the MOSFET degrade the ability of the gate of the same to control whether the device is on or off. This phenomenon is called the “short-channel effect” (SCE).
A conventional SRAM cell is comprised of first and second driver transistors whose drain-source paths are respectively connected between first and second storage nodes and ground, first and second load elements connected between the first and second storage nodes and power supply, respectively, first and second switching transistors whose drain-source paths are respectively connected between the first and second storage nodes and a pair of data lines (or bit lines). Gates of the first and second driver transistors are connected to the second and first storage nodes, respectively, and gates of the first and second switching transistors are connected to a word line.
SRAM cells may generally be classified according to the manufacturing configuration of the load elements used in the cells. A high resistance SRAM cell uses as load elements layers of high-resistance material such as polycrystalline silicon (typically called “polysilicon”) on an insulating layer over a semiconductor substrate in which the first and second driver transistors and the first and second switching transistors are formed. A thin-film SRAM cell uses as load elements thin-film transistors on an insulating layer over the semiconductor substrate on which the four transistors are formed. In a CMOS SRAM cell, first and second load transistors complementary to the first and second driver transistors are formed on the semiconductor substrate together with the other transistors.
With the scaling down of the manufacturing technology, what is needed is an improved SRAM that may be efficiently constructed.